1. Field of the Invention
This invention relates to a semiconductor memory device. More specifically, this invention relates to a nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate.
2. Description of the Related Art
NOR and NAND flash memories have been widely used as nonvolatile semiconductor memory devices.
In recent years, a flash memory combining the features of the NOR flash memory and the NAND flash memory has been proposed. This type of flash memory has been disclosed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. A flash memory of this type (hereinafter, referred to as a 2Tr flash memory) has memory cells each of which includes two MOS transistors. In such a memory cell, one MOS transistor, which functions as a nonvolatile memory section, includes a control gate and a floating gate and is connected to a bit line. The other MOS transistor, which is connected to a source line, is used to select a memory cell.
In semiconductor memory, such as flash memory, redundancy techniques have been widely used to improve the production yield. In the redundancy techniques, redundancy elements are provided in addition to ordinary elements (e.g., memory cells, word lines, column select lines, or I/O lines). If a fault has taken place, ordinary elements are replaced with redundancy elements, thereby remedying the fault. “Redundancy” originally means “an excess of requirements.” However, as the technique of replacing defective parts with redundancy elements has been popularized, the technique itself has been called “redundancy technique.” Therefore, let the word “redundancy” in this specification mean “a measure to remedy defective parts by using redundancy lines, redundancy cells, or the like.”
With the conventional redundancy techniques, however, the power consumption in a read operation is high.